The present invention relates to a display device driving circuit, and more particularly to a driving circuit for a liquid crystal display device used in a dot inversion driving mode.
Liquid crystal display (LCD) devices are now a major class of image display devices for they have a reduced power consumption and take less space as compared with CRTs, etc. Among the various types of liquid crystal display devices, those of an active matrix type using TFTs (Thin Film Transistors) are used as personal computer displays and TV screens, as they have high definitions and can be made in large screen sizes.
FIG. 14 is a circuit diagram illustrating a conventional full-color liquid crystal display device.
As illustrated in FIG. 14, the conventional liquid crystal display device includes a signal line driving circuit 110, a scanning line driving circuit 112 and a display section (liquid crystal panel).
The display section includes a plurality of signal lines 152a, 152b, 152c, . . . , (hereinafter referred to collectively as “signal lines 152”) extending in the column direction (the vertical direction in the figure) from the signal line (source) driving circuit 110, a plurality of scanning lines (gate lines) 151a, 151b, 151c, . . . , (hereinafter referred to collectively as “scanning lines 151”) extending in the row direction (the horizontal direction in the figure) from the scanning line (gate line) driving circuit 112, and sub-pixels 153 arranged in a matrix pattern. Each sub-pixel 153 is located near one of a plurality of intersections between the signal lines 152 and the scanning lines 151. Moreover, each sub-pixel 153 includes a liquid crystal cell 155, a hold condenser 156 and a TFT 154. The liquid crystal material in the liquid crystal cell 155 is interposed between a pixel electrode and a counter electrode. Herein, the term “sub-pixel” is used to refer to a component of one pixel, and each sub-pixel is used to produce one of the following colors: red (R), green (G) and blue (B).
The signal line driving circuit 110 is normally a multiple-output integrated circuit, and supplies output voltages Vout1, Vout2, Vout3, . . . , to the source electrodes of the TFTs 154. Note that although transfer gates TG101a, TG101b, . . . , are shown in FIG. 14 to be outside the adjacent signal line driving circuit 110, they are actually provided inside the signal line driving circuit 110. Nevertheless, the transfer gates TG101a, TG101b, . . . , may alternatively be provided on the panel side. Each transfer gate TG101 electrically connects output sections of the signal line driving circuit 110 with each other, as will be described later.
Moreover, also the scanning line driving circuit 112 is normally a multiple-output integrated circuit, and supplies output voltages to the gate electrodes of the TFTs 154.
In the liquid crystal display device, the scanning line driving circuit 112 selects the sub-pixels 153 by rows while the signal line driving circuit 110 supplies an image-forming signal in the form of a voltage. Note that for full-color display, signal lines 152 include groups of signal lines for R (red), G (green) and B (blue).
In a liquid crystal display device as described above, an after-image phenomenon called “burn-in” occurs if a DC voltage is applied over a long period of time. Therefore, it is necessary to invert the voltage applied across the liquid crystal material at predetermined intervals. Such a driving mode is called “frame inversion driving mode”.
The frame inversion driving mode includes a line inversion driving mode, a dot inversion driving mode, etc.
A dot inversion driving mode is a driving mode in which voltages of opposite polarities are applied to adjacent sub-pixels, and is capable of better suppressing flicker on the screen than with the line inversion driving mode.
FIG. 15 illustrates a portion of a conventional signal line driving circuit employing a dot inversion driving mode. Particularly, FIG. 15 illustrates the output circuit of the signal line driving circuit.
Image-forming signals and gray scale signals are input to the signal line driving circuit from an image signal processing circuit (not shown) and a gray scale voltage generation circuit (not shown), respectively. Then, output voltages Vout1, Vout2, . . . , according to the gray scale signals are output from the output circuit of the signal line driving circuit.
As illustrated in FIG. 15, the output circuit of the conventional signal line driving circuit includes operational amplifiers Amp101 and Amp102, output sections out1 and out2, a voltage supply line S1 connecting the output section of the operational amplifier Amp101 to the output section out1, a voltage supply line S2 connecting the output section of the operational amplifier Amp102 to the output section out2, a switch SW1 provided along the voltage supply line S1, a switch SW2 provided along the voltage supply line S2, and the transfer gate TG101 provided between the voltage supply line S1 and the voltage supply line S2 for shorting the output section out1 with the output section out2. Although only two adjacent output sections are shown in the figure, an actual output circuit includes an array of multiple output sections connected to multiple voltage supply lines.
Next, the operation and the function of the conventional signal line driving circuit will be described.
FIG. 16 is a timing chart illustrating voltage transitions at various points in the conventional output circuit.
As illustrated in FIG. 16, in a dot inversion driving mode, voltages Vout1 and Vout2 of the adjacent output sections out1 and out2 are voltages of opposite polarities with respect to a common voltage Vcom. The polarities of the output sections out1 and out2 are inverted with respect to Vcom for every horizontal scanning period H.
When driving the liquid crystal display device, the parasitic capacitance of the signal line 152 illustrated in FIG. 14, the capacitance of the hold condenser 156, the liquid crystal capacitance of the liquid crystal cell 155, etc., occur as load capacitances. The current for driving the load capacitances constitutes a part of the total power consumption of the liquid crystal display device. In view of this, the conventional signal line driving circuit includes the switches SW1 and SW2, and the transfer gate TG101 for shorting the adjacent output sections out1 and out2 with each other, so as to reduce the power consumption. The effect of reducing the power consumption will now be described along with the description of the operation of the circuit.
With the conventional signal line driving circuit employing a dot inversion driving mode, the horizontal scanning period H includes a period B and a period A, as illustrated in FIG. 16.
First, in a horizontal scanning period H1, when the polarities of output voltages Vo1 and Vo2 of the operational amplifiers Amp101 and Amp102 transition from (+) and (−) to (−) and (+), respectively, the switches SW1 and SW2 are both turned OFF during the period B. During the period B, the transfer gate TG101 is turned ON, thereby electrically shorting the output section out1 with the output section out2. Moreover, during the period B, the polarity of the output voltage Vo1 of the operational amplifier Amp101 transitions to (−), and that of the output voltage Vo2 of the operational amplifier Amp102 transitions to (+).
On the panel side, there are load capacitances connected respectively to the output sections out1 and out2. The load connected to the output section out1 whose output voltage has been (+) until immediately before the period B has a larger charge than the load connected to the output section out2. Therefore, with the transfer gate TG101 being ON, a current I flows from the load connected to the output section out1 to the load connected to the output section out2 during the period B. In this period, the switches SW1 and SW2 are OFF, whereby the potential of the output section out1 can be brought closer to that of the output section out2 without consuming power.
Next, in the period A, the switches SW1 and SW2 are both turned ON, and the transfer gate TG101 is turned OFF. Thus, as illustrated in FIG. 16, the output sections of the operational amplifiers Amp101 and Amp102 are connected respectively to the output sections out1 and out2. Then, the load connected to the output section out1 discharges a current flowing from the output section out1 to the operational amplifier Amp101, and the load connected to the output section out2 is charged with the current flowing from the operational amplifier Amp102 to the output section out2. Thus, Vout1 and Vout2 are turned (−) and (+), respectively, with a slight delay from the start of the period A.
In the period A, a current flows through the operational amplifiers Amp101 and Amp102, thereby consuming some power. However, the power consumption can be reduced because the charge is distributed between adjacent loads in the liquid crystal display device in the period B.
This effect is obtained also in the following period, i.e., a horizontal scanning period H2. Specifically, in the period B, the switches SW1 and SW2 are turned OFF, and the transfer gate TG101 is turned ON, whereby the current I flows through the transfer gate TG101 in the direction opposite to that during the horizontal scanning period H1, and the charge is distributed from the load connected to the output section out2 to the load connected to the output section out1.
Then, during the period A in the horizontal scanning period H2, the switches SW1 and SW2 are turned ON, and the transfer gate TG101 is turned OFF. Thus, the load connected to the output section out1 is charged with the current output from the operational amplifier Amp101, and the load connected to the output section out2 discharges a current flowing from the output section out2 to the operational amplifier Amp102.
The operation as described above is repeated in the conventional signal line driving circuit.
As described above, the conventional signal line driving circuit aims at conserving power in a dot inversion driving mode. Such a configuration where outputs of a signal line driving circuit are shorted with each other is described in, for example, Japanese Laid-Open Patent Publication Nos. 11-95729 and 2000-39870.
FIG. 17 is a block diagram schematically illustrating the mask layout of the output circuit in the conventional signal line driving circuit.
The conventional signal line driving circuit described above is provided in the form of a single chip onto which about 384 outputs, for example, are integrated.
The circuit layout is as illustrated in FIG. 17. When there are n outputs (where n is a natural number), n operational amplifiers are arranged in a row, and the output sections connected respectively to the adjacent operational amplifiers are arranged in a row in the same order as that of the operational amplifiers. One transfer gate for shorting output sections with each other is provided for each pair of operational amplifiers, and the transfer gates are arranged in the same order as those of the operational amplifiers and the output sections.
Note that in a full-color liquid crystal display device, these components are arranged in a repeating pattern of three colors, e.g., R-G-B-R-G-B . . . . Therefore, in the conventional signal line driving circuit, output sections of different colors are shorted with each other, e.g., R (red) with G (green), or B (blue) with R.
As illustrated in FIG. 16, with the conventional signal line driving circuit, the charge of a load can be effectively distributed if the voltages Vout1 and Vout2 both reach equilibrium within an amount of time that is sufficiently shorter than the period B.
However, in a liquid crystal display device having a large size, for example, a signal line has a large load capacitance, and a longer time is required for charging. In such a case, the period B ends before Vout1 and Vout2 reach equilibrium, whereby the charge of the load is not sufficiently redistributed. Therefore, the amount of charge supplied from the signal line driving circuit increases, thereby decreasing the effect of reducing the power consumption.
If the amount of charge supplied from the signal line driving circuit increases, an increasing amount of heat is generated in the IC chip of the signal line driving circuit, whereby the circuit operation may be hindered by heat.
Moreover, in the conventional signal line driving circuit, output sections of different colors are shorted with each other, whereby the power consumption reducing effect is not sometimes obtained sufficiently depending on the image being displayed on the screen.
For example, in a case where an R output section (i.e., an output section through which R level data is output) and a G output section (i.e., an output section through which G level data is output) are shorted with each other, although the power consumption is reduced in a solid white display or a solid black display where the R level and the G level are equal to each other, the power consumption is not sufficiently reduced in a solid red display.
As described above, with the conventional signal line driving circuit, there is still a room for further reduction in the power consumption. Particularly, the power consumption reducing effect may not be sufficient for cases where the load capacitance on the panel side is large.